`timescale 1 ns / 100 ps		//modify the parameters accordingly

module MyDFF_tb;

	reg clk;
	reg rst_n;
	reg d;
	wire q_out;

	MyDFF dut (
		rst_n,
		clk,
		d,
		q_out
	);

	initial begin
		clk = 0;
		forever #10 clk = ~clk;	// like 50MHz
	end

	initial begin
		d = 0;
		rst_n = 0;
		#20;
		rst_n = 1;
		
		#20 d = 1;
		#20 d = 0;
		#20 d = 1;
		#20 rst_n = 0;
		#20 rst_n = 1;
		#20 d = 1;
		#20 d = 0;
		#20 d = 0;

		#20 $stop;
	end

endmodule
